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| 42011hkim 20110311-s00003 no.a1909-1/32 ver.2.01 LC87F1M16A overview the LC87F1M16A is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 16k-byte flash rom (onboard programmable), 1024-byte ram, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time- of-day clock, two channels of synchronous sio interface (with automatic block transmi ssion/reception capabilities), an asynchronous/synchr onous sio interface, a uart inte rface (full duplex), a uart in terface with smar tcard interface function (full duplex), a full-speed usb in terface (function), a 12-bit 20-channel ad converter (12- or 8-bit resolution selectable), 2 channels of 12-bit pwm, a system clock frequency divider, an internal reset and a 35-source 10-vector interrupt feature. features ? flash rom ? capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5v ? block-erasable in 128 byte units ? writes data in 2-byte units ? 16384 8 bits ? ram ? 1024 9 bits ? bus cycle time ? 83.3ns (when cf=12mhz) note: the bus cycle time here refers to the rom read speed. ordering number : ena1909a cmos ic 16k-byte from and 1024-byte ram integrated 8-bit 1-chip microcontroller with full-speed usb * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F1M16A no.a1909-2/32 ? minimum instruction cycle time (tcyc) ? 250ns (when cf=12mhz) ? ports ? i/o ports ports whose i/o direction can be designated in 1-bit units 35 (p00 to p07, p10 to p17, p20 to p27, p31 to p34, p70 to p73, pwm0, pwm1, xt2) ? usb ports 2 (d+, d-) ? dedicated oscillator ports 2 (cf1, cf2) ? input-only port (also used for oscillation) 1 (xt1) ? reset pins 1 ( res ) ? dedicated debugger port 1 (owp0) ? power supply pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with 2 capture registers. mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescal er (with toggle out puts) + 8-bit timer/ counter with an 8-bit pres caler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a pwm output) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer (1) the clock is selectable from the subclock (32.768khz cr ystal oscillation), system clock, and timer 0 prescaler output. (2) interrupts programmable in 5 different time schemes ? sio ? sio0: synchronous serial interface (1) lsb first/msb first mode selectable (2) transfer clock cycle: 4/3 to 512/3 tcyc (3) automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio4: synchronous serial interface (1) lsb first/msb first mode selectable (2) transfer clock cycle: 4/3 to 1020/3 tcyc (3) automatic continuous data transmission (1 to 1024 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) (4) clock polarity selectable (5) crc16 calculator circuit built in LC87F1M16A no.a1909-3/32 ? full duplex uart ? uart1 (1) data length : 7/8/9 bits selectable (2) stop bits : 1 bit (2 bits in continuous transmission mode) (3) baud rate : 16/3 to 8192/3 tcyc ? scuart (1) data length : 7/8 bits selectable (2) stop bits : 1/2 bits selectable (3) parity bits : none/even parity/odd parity (4) baud rate : 8/3 to 8192/3 tcyc (5) lsb first/msb first mode delectable (6) smartcard interface function ? ad converter: 12 bits 20 channels ? 12-/8-bit resolution selectable ad converter ? pwm: multifrequency 12-bit pwm 2 channels ? usb interface (function controller) (1) compliant with usb 2.0 full-speed (2) supports a maximum of 6 user-defined endpoints. endpoint ep0 ep1 ep2 ep3 ep4 ep5 ep6 control { - - - - - - bulk - { { { { { { interrupt - { { { { { { transfer type isochronous - { { { { { { max. payload 64 64 64 64 64 64 64 ? watchdog timer ? internal counter watchdog timer (1) generates an internal reset on an overflow occurring in the timer running on the low-speed rc oscillator clock (approx. 30khz) or subclock. (2) operating mode at halt/hold mode is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) ? clock output function (1) can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. (2) can output the source oscillation clock for the subclock. LC87F1M16A no.a1909-4/32 ? interrupts ? 35 sources, 10 vector addresses (1) provides three levels (low (l), hi gh (h), and highest (x)) of multiplex inte rrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. (2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/ int4/usb bus active 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/usb bus reset/usb susp end/uart1 receive complete/ scuart receive complete 8 0003bh h or l sio1/usb endpoint/usb-sof/sio4/ uart1 buffer empty/uart1 transmit complete/ scuart buffer empty/scuart transmit complete 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/pwm0/pwm1/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 512 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits ( 5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits ( 8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation and pll circuits ? rc oscillation circuit (internal) : for system clock (approx. 1mhz) ? low-speed rc oscillation circuit (internal) : for watchdog timer (approx. 30khz) ? cf oscillation circuit : for system clock ? crystal oscillation circuit : for system clock, time-of-day clock ? pll circuit (internal) : for usb interface (see fig.5) ? internal reset circuit ? power-on reset (por) function (1) por reset is generated only at power-on time. (2) the por release level can be selected from 4 levels (2.57v, 2.87v, 3.86v and 4.35v) through option configuration. ? low-voltage detection reset (lvd) function (1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. (2) the use/disuse of the lvd function and the voltage threshold level can be selected from 3 levels (2.81v, 3.79v and 4.28v) through option configuration. LC87F1M16A no.a1909-5/32 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (1) oscillation is not halted automatically. (2) there are three ways of resetting the hold mode. 1) setting the reset pin to the lower level 2) having the watchdog timer or lvd function generate a reset 3) having an interrupt generated ? hold mode: suspends instruction execution and the operation of the peripheral circuits. (1) the pll base clock generator, cf, rc and cr ystal oscillators automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. (2) there are five ways of resetting the hold mode. 1) setting the reset pin to the lower level 2) having the watchdog timer or lvd function generate a reset 3) having an interrupt source established at one of the int0, int1, int2, int4 or int5 pins * int0 and int1 hold mode reset is available only when level detection is set. 4) having an interrupt source established at port 0 5) having an bus active interrupt source established in the usb interface circuit ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. (1) the pll base clock generator, cf and rc oscillator automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. (2) the state of crystal oscillation established when the x'tal hold mode is entered is retained. (3) there are six ways of resetting the x'tal hold mode. 1) setting the reset pin to the low level 2) having the watchdog timer or lvd function generate a reset 3) having an interrupt source established at either int0, int1, int2, int4 or int5 * int0 and int1 hold mode reset is available only when level detection is set. 4) having an interrupt source established at port 0 5) having an interrupt source established in the base timer circuit 6) having an bus active interrupt source established in the usb interface circuit ? package form ? sqfp48 (7 7): lead-/halogen-free type ? development tools ? on-chip debugger: tcb87 type-c (one wire communication cable) + LC87F1M16A LC87F1M16A no.a1909-6/32 ? flash rom programming boards package programming boards sqfp48(7 7) w87f55256sq ? flash programmer maker model supported version device flash support group, inc. (fsg) single programmer af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 03.32 or later 87f016ju af9101/af9103(main unit) (fsg models) flash support group, inc. (fsg) + sanyo (note 1) onboard single/gang programmer sib87(inter face driver) (sanyo model) (note 2) LC87F1M16A single/gang programmer skk/skk type b (sanyofws) sanyo onboard single/gang programmer skk-dbg type c (sanyofws) application version 1.06 or later chip data version 2.31 or later lc87f1m16 for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information. LC87F1M16A no.a1909-7/32 package dimensions unit : mm (typ) 3163b pin assignment sanyo: sqfp48(7 7) ?lead-/halogen-free type? sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 d- d+ v dd 3 v ss 3 p34/ufilt p33 p32/scrx p31/sctx owp0 p70/int0/t0lcp/dpup p71/int1/t0hcp p72/int2/t0in 24 23 22 21 20 19 18 17 16 15 14 13 p03/an3 p02/an2/tdn2 p01/an1/tdp1 p00/an0/tdn1 v ss 2 v dd 2 pwm0/an9/tdp0 pwm1/an8/tdn0 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 37 38 39 40 41 42 43 44 45 46 47 48 LC87F1M16A top view p27/int5/an19/dpup2 p26/int5/an18 p25/int5/an17 p24/int5/int7/an16/sck4 p23/int4/an15/si4 p22/int4/an14/so4 p21/int4/an13/urx1 p20/int4/int6/an12/utx1 p07/an7/t7o p06/an6/t6o p05/an5/cko p04/an4 p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 LC87F1M16A no.a1909-8/32 sqfp48 name sqfp48 name 1 p73/int3/t0in 25 p04/an4 2 res 26 p05/an5/cko 3 xt1/an10 27 p06/an6/t6o 4 xt2/an11 28 p07/an7/t7o 5 v ss 1 29 p20/int4/int6/an12/utx1 6 cf1 30 p21/int4/an13/urx1 7 cf2 31 p22/int4/an14/so4 8 v dd 1 32 p23/int4/an15/si4 9 p10/so0 33 p24/int5/int7/an16/sck4 10 p11/si0/sb0 34 p25/int5/an17 11 p12/sck0 35 p26/int5/an18 12 p13/so1 36 p27/int5/an19/dpup2 13 p14/si1/sb1 37 d- 14 p15/sck1 38 d+ 15 p16/t1pwml 39 v dd 3 16 p17/t1pwmh/buz 40 v ss 3 17 pwm1/an8/tdn0 41 p34/ufilt 18 pwm0/an9/tdp0 42 p33 19 v dd 2 43 p32/scrx 20 v ss 2 44 p31/sctx 21 p00/an0/tdn1 45 owp0 22 p01/an1/tdp1 46 p70/int0/t0lcp/dpup 23 p02/an2/tdn2 47 p71/int1/t0hcp 24 p03/an3 48 p72/int2/t0in LC87F1M16A no.a1909-9/32 system block diagram interrupt control from standby control clock generator cf x?tal rc ir pla pc bus interface port 0 port 1 acc b register c register alu psw rar ram stack pointer watchdog timer base timer timer 4 pwm1 int0 to int7 noise filter sio0 port 2 usb pll port 7 port 3 adc sio1 timer 0 timer 1 pwm0 timer 5 timer 6 timer 7 uart1 on-chip debugger usb interface sio4 scuart high current driver LC87F1M16A no.a1909-10/32 pin description pin name i/o description option v ss 1,v ss 2, v ss 3 - - power supply no v dd 1, v dd 2 - + power supply no v dd 3 - usb reference voltage yes port 0 p00 to p07 i/o ? 8-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? hold reset input ? port 0 interrupt input ? pin functions ad converter input ports: an0 to an7(p00 to p07) p00: high current nch driver(tdn1) p01: high current pch driver(tdp1) p02: high current nch driver(tdn2) p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output/beeper output yes port 2 ? 8-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions ad converter input ports: an12 to an19(p20 to p27) p20 to p23: int4 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p20: int6 input/timer 0l ca pture 1 input/uart1 transmit p21: uart1 receive p22: sio4 date i/o p23: sio4 date i/o p24: int7 input/timer 0h capture 1 input/sio4 clock i/o p27: d+ 1.5k pull-up resistor connect pin interrupt acknowledge types rising falling rising & falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable int6 enable enable enable disable disable int7 enable enable enable disable disable p20 to p27 i/o yes port 3 p31 to p34 i/o ? 4-bit i/o ports ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p31: scuart transmit p32: scuart receive p34: usb interface pll filter pin (see fig. 5.) yes continued on next page. LC87F1M16A no.a1909-11/32 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p70: int0 input/hold reset input/ timer 0l capture input/ d+ 1.5k pull-up resistor connect pin p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (input with noise filter) /timer 0 event input/timer 0h capture input interrupt acknowledge types rising falling rising & falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o no pwm0 pwm1 i/o ? pwm0, pwm1 output port ? pin functions general-purpose input ports ad converter input ports: an8(pwm1), an9(pwm0) pwm0: high current pch driver(tdp0) pwm1: high current nch driver(tdn0) no d- i/o ? usb data i/o pin d- ? general-purpose i/o port no d+ i/o ? usb data i/o pin d+ ? general-purpose i/o port no res input external reset input/internal reset output pin no xt1 input ? 32.768khz crystal oscillator input ? pin functions general-purpose input port ad converter input ports: an10 no xt2 i/o ? 32.768khz crystal oscillator output ? pin functions general-purpose i/o ad converter input port: an11 no cf1 input ceramic resonator input no cf2 output ceramic resonator output no owp0 i/o dedicated debugger port no LC87F1M16A no.a1909-12/32 on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled ?rd87 on-chip debugger installation manual? recommended unused pin connections recommended unused pin connections port name board software p00 to p07 open output low p10 to p17 open output low p20 to p27 open output low p31 to p34 open output low p70 to p73 open output low pwm0, pwm1 open output low d+, d- open output low xt1 pulled low with a 100k resistor or less - xt2 open output low owp0 pulled low with a 100k resistor - note: p34 and ufilt share the same pin, so if usb function is used, the pin must be set to input mode. port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable p00 to p07 p10 to p17 p20 to p27 p31 to p34 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no d+, d- - no cmos no xt1 - no input only no xt2 - no 32.768khz crystal resonator output (n channel open drain when in general-purpose output mode) no LC87F1M16A no.a1909-13/32 user option table option name option type flash version opti on selected in units of option selection cmos p00 to p07 enable 1 bit nch-open drain cmos p10 to p17 enable 1 bit nch-open drain cmos p20 to p27 enable 1 bit nch-open drain cmos port output form p31 to p34 enable 1 bit nch-open drain 00000h program start address - enable - 03e00h use usb regulator enable - nonuse use usb regulator (at hold mode) enable - nonuse use usb regulator usb regulator (at halt mode) enable - nonuse enable main clock 8mhz selection - enable - disable enable: use detect function enable - disable: not used low-voltage detection reset function detect level enable - 3-level power-on reset function power-on reset level enable - 4-level LC87F1M16A no.a1909-14/32 usb reference power option when a voltage 4.5 to 5.5v is supplied to v dd 1 and the internal usb reference voltage circuit is activated, the reference voltage for usb port output is generated. the ac tive/inactive state of the reference voltage circuit can be switched by option select. the procedure for marking the option selection is described below. (1) (2) (3) (4) usb regulator use use use nonuse usb regulator at hold mode use nonuse nonuse nonuse option settings usb regulator at halt mode use nonuse use nonuse normal mode active active active inactive hold mode active inactive inactive inactive reference voltage circuit state halt mode active inactive active inactive ? when the usb reference voltage circuit is made inactive, th e level of the reference voltage for usb port output is equal to v dd 1. ? selection (2) or (3) can be used to set the reference voltage circuit inactive in hold or halt mode. ? when the reference voltage circuit is activated, the current drain increases by approximately 100 a compared with when the reference voltage circuit is inactive. example 1: v dd 1=v dd 2=3.3v ? inactivating the reference voltage circuit (selection (4)). ? connecting v dd 3 to v dd 1 and v dd 2. example 2: v dd 1=v dd 2=5.0v ? activating the reference volta ge circuit (selection (1)). ? isolating v dd 3 from v dd 1 and v dd 2, and connecting capacitor between v dd 3 and v ss . v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply 3.3v lsi d+ d- ufilt to usb connector 27 to 33 5pf 0 2.2 p70/p27 2.2 2.2 5pf 1.5k p70/p27 2.2 LC87F1M16A no.a1909-15/32 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1= v dd 2= v dd 3 -0.3 +6.5 input voltage v i (1) xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7 pwm0, pwm1 xt2 -0.3 v dd +0.3 v ioph(1) p00, p02 to p07 ports 1, 2 ? when cmos output type is selected ? per 1 applicable pin -10 ioph(2) pwm1 per 1 applicable pin -20 ioph(3) pwm0(tdp0) p01(tdp1) ? when cmos output type is selected ? per 1 applicable pin -50 peak output current ioph(4) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -5 iomh(1) p00, p02 to p07 ports 1, 2 ? when cmos output type is selected ? per 1 applicable pin -7.5 iomh(2) pwm1 per 1 applicable pin -15 iomh(3) pwm0(tdp0) p01(tdp1) ? when cmos output type is selected ? per 1 applicable pin -30 average output current (note 1-1) iomh(4) port 3 p71 to p73 ? when cmos output type is selected ? per 1 applicable pin -3 ioah(1) p00, p02 to p07 ports 2 total current of all applicable pins -25 ioah(2) port 1 pwm1 total current of all applicable pins -25 ioah(3) pwm0(tdp0) p01(tdp1) total current of all applicable pins -50 ioah(4) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins -100 ioah(5) port 3 p71 to p73 total current of all applicable pins -10 high level output current total output current ioah(6) d+, d- total current of all applicable pins -25 ma note 1-1: the average output current is an average of current values measured over 100ms intervals. continued on next page. LC87F1M16A no.a1909-16/32 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit iopl(1) p03 to p07 ports 1, 2 pwm0 per 1 applicable pin 20 iopl(2) p01 per 1 applicable pin 30 iopl(3) pwm1(tdn0) p00(tdn1) p02(tdn2) per 1 applicable pin 50 peak output current iopl(4) ports 3, 7 xt2 per 1 applicable pin 10 ioml(1) p03 to p07 ports 1, 2 pwm0 per 1 applicable pin 15 ioml(2) p01 per 1 applicable pin 20 ioml(3) pwm1(tdn0) p00(tdn1) p02(tdn2) per 1 applicable pin 30 average output current (note 1-1) ioml(4) ports 3, 7 xt2 per 1 applicable pin 7.5 ioal(1) p01, p03 to p07 ports 2 total current of all applicable pins 45 ioal(2) port 1 pwm0 total current of all applicable pins 45 ioal(3) pwm1(tdn0) p00(tdn1) p02(tdn2) total current of all applicable pins 50 ioal(4) ports 0, 1, 2 pwm0, pwm1 total current of all applicable pins 140 ioal(5) ports 3, 7 xt2 total current of all applicable pins 15 low level output current total output current ioal(6) d+, d- total current of all applicable pins 25 ma ta=-30 to +70 c 190 allowable power dissipation pd max sqfp48(7 7) ta=-40 to +85 c 140 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c note 1-1: the average output current is an average of current values measured over 100ms intervals. LC87F1M16A no.a1909-17/32 allowable operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0.245 s tcyc 200 s 3.0 5.5 0.490 s tcyc 200 s except in onboard programming mode 2.7 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.245 s cyc 0.383 s usb circuit active 3.0 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) port 0, 1, 2, 3, 7 pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd high level input voltage v ih (2) xt1, xt2, cf1, res 2.7 to 5.5 0.75v dd v dd v il (1) 4.0 to 5.5 v ss 0.1v dd +0.4 v il (2) port 1, 2, 3, 7 2.7 to 4.0 v ss 0.2v dd v il (3) 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) port 0 pwm0, pwm1 2.7 to 4.0 v ss 0.2v dd low level input voltage v il (5) xt1, xt2, cf1, res 2.7 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.245 200 except for onboard programming mode 2.7 to 5.5 0.490 200 instruction cycle time (note 2-2) tcyc usb circuit active 3.0 to 5.5 0.245 0.383 s ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 3.0 to 5.5 0.1 12 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.7 to 5.5 0.1 6 mhz fmcf cf1, cf2 when 12m hz ceramic oscillation see fig. 1. 3.0 to 5.5 12 fmrc internal rc oscillation 2.7 to 5.5 0.5 1.0 2.0 mhz fmslrc internal low-speed rc oscillation 2.7 to 5.5 15 30 60 oscillation frequency range (note 2-3) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.7 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. LC87F1M16A no.a1909-18/32 electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3, 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) xt1, xt2 input port configuration v in =v dd 2.7 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.7 to 5.5 15 i il (1) ports 0, 1, 2, 3, 7 res pwm0, pwm1 d+, d- output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2 input port configuration v in =v ss 2.7 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.7 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 p71 to p73 i oh =-0.2ma 2.7 to 5.5 v dd -0.4 v oh (4) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (5) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (6) pwm0, wm1 p05(cko when using system clock output function) i oh =-1ma 2.7 to 5.5 v dd -0.4 high level output voltage v oh (7) pwm0, p01 (when using high current driver) i oh =-30ma 4.5 to 5.5 v dd -0.5 v dd -0.15 v ol (1) i ol =30ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 0.4 v ol (3) p00, p01 i ol =2.5ma 2.7 to 5.5 0.4 v ol (4) i ol =10ma 4.5 to 5.5 1.5 v ol (5) i ol =1.6ma 3.0 to 5.5 0.4 v ol (6) ports 0, 1, 2 pwm0, pwm1 xt2 i ol =1ma 2.7 to 5.5 0.4 v ol (7) i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) ports 3, 7 i ol =1ma 2.7 to 5.5 0.4 low level output voltage v ol (9) pwm1, p00, p02 (when using high current driver) i ol =30ma 4.5 to 5.5 0.15 0.5 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3, 7 v oh =0.9v dd 2.7 to 5.5 18 50 150 k hysteresis voltage vhys res port 1, 2, 3, 7 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.7 to 5.5 10 pf LC87F1M16A no.a1909-19/32 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 8. 1 tsckha(1a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? see fig. 8. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transmission/ reception mode ? usb is in use simultaneous ? sio4 is not in use simultaneous. ? see fig. 8. ? (note 4-1-2) 7 input clock high level pulse width tsckha(1c) sck0(p12) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? see fig. 8. ? (note 4-1-2) 2.7 to 5.5 9 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 8. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? usb nor sio4 are not in use simultaneous. ? cmos output selected ? see fig. 8. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tsckha(2b) ? continuous data transmission/ reception mode ? usb is in use simultaneous ? sio4 is not in use simultaneous. ? cmos output selected ? see fig. 8. tsckh(2) +2tcyc tsckh(2) +(19/3) tcyc serial clock output clock high level pulse width tsckha(2c) sck0(p12) ? continuous data transmission/ reception mode ? usb and sio4 are in use simultaneous. ? cmos output selected ? see fig. 8. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) +(25/3) tcyc tcyc note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. continued on next page. LC87F1M16A no.a1909-20/32 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit data setup time tsdi(1) 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.03 tdd0(1) ? continuous data transmission/ reception mode ? (note 4-1-3) (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.05 s note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 8. 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 8. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? when cmos output type is selected ? see fig. 8. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) (1/3)tcyc +0.01 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 8. 2.7 to 5.5 0.01 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 8. 2.7 to 5.5 (1/2)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. LC87F1M16A no.a1909-21/32 3. sio4 serial i/o characteristics (note 4-3-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit frequency tsck(5) 2 low level pulse width tsckl(5) 1 tsckh(5) see fig.8. 1 tsckha(5a) ? usb nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? see fig.8. ? (note 4-3-2) 4 tsckha(5b) ? usb is in use simultaneous. ? do not use sio0 continuous data transmission mode at the same time. ? see fig.8. ? (note 4-3-2) 7 input clock high level pulse width tsckha(5c) sck4(p24) ? usb and continuous data transmission/ reception mode of sio0 are in use simultaneous. ? see fig.8. ? (note 4-3-2) 2.7 to 5.5 10 frequency tsck(6) 4/3 tcyc low level pulse width tsckl(6) 1/2 tsckh(6) ? cmos output selected ? see fig.8 1/2 tsck tsckha(6a) ? usb nor continuous data transmission/reception mode of sio0 are not in use simultaneous. ? cmos output selected ? see fig.8. tsckh(6) +(5/3) tcyc tsckh(6) +(10/3) tcyc tsckha(6b) ? usb is in use simultaneous. ? do not use sio0 continuous data transmission mode at the same time. ? cmos output selected ? see fig8. tsckh(6) +(5/3) tcyc tsckh(6) +(19/3) tcyc serial clock output clock high level pulse width tsckha(6c) sck4(p24) ? usb and continuous data transmission/reception mode of sio0 are in use simultaneous. ? cmos output selected ? see fig.8. 2.7 to 5.5 tsckh(6) +(5/3) tcyc tsckh(6) +(28/3) tcyc tcyc data setup time tsdi(3) 2.7 to 5.5 0.03 serial input data hold time thdi(3) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? see fig.8. 2.7 to 5.5 0.03 s note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input in continuous trans/rec mode, a time from si4run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. continued on next page. LC87F1M16A no.a1909-22/32 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit serial output output delay time tdd0(5) so4(p22), si4(p23) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig.8. 2.7 to 5.5 (1/3)tcyc +0.05 s pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tp1h(1) tp1l(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are nabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc high/low level pulse width tpil(5) res resetting is enabled. 2.7 to 5.5 200 s LC87F1M16A no.a1909-23/32 ad converter characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v <12-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb 4.5 to 5.5 32 115 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07), an8(pwm1), an9(pwm0), an10(xt1), an11(xt2), an12(p20) to an19(p27) vain=v ss 3.0 to 5.5 -1 a <8-bits ad converter mode> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 20 90 conversion time tcad see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 90 s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p00) to an7(p07), an8(pwm1), an9(pwm0), an10(xt1), an11(xt2), an12(p20) to an19(p27) vain=v ss 3.0 to 5.5 -1 a conversion time calculation formulas : 12-bits ad converter mode : tcad (conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8-bits ad converter mode : tcad (conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc LC87F1M16A no.a1909-24/32 power-on reset (por) characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions option selected voltage min typ max unit 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 por release voltage porrl select from option (note 7-1) 4.35v 4.21 4.35 4.49 detection voltage unknown state pouks see fig.11 (note 7-2) 0.7 0.95 v power supply rise time poris power supply rise time from 0v to 1.6v 100 ms note 7-1: the por release level can be selected out of 4 levels only when the lvd reset function is disabled. note 7-2: por is in unknown state before transistor start operation. low voltage detection reset (lvd) characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions option selected voltage min typ max unit 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 lvd reset voltage (note 8-2) lvdet 4.28v 4.18 4.28 4.38 v 2.81v 55 3.79v 60 lvd hysteresis width lvhys select from option see fig.12 (note 8-1) (note 8-3) 4.28v 60 mv detection voltage unknown state lvuks see fig.12 (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity). tlvdw lvdet-0.5v see fig.13 0.2 ms note 8-1: the lvd reset level can be selected out of 3 levels only when the lvd reset function is enabled. note 8-2: lvd reset voltage specification values do not include hysteresis voltage. note 8-3: lvd reset voltage may exceed its specification values when port out put state changes and and/or when a large current flows through port. note 8-4: lvd is in unknown state before transistor start operation. LC87F1M16A no.a1909-25/32 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 8.8 16 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 5.1 9.2 iddop(3) 4.5 to 5.5 13 23 iddop(4) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 3.0 to 3.6 7.0 13 iddop(5) 4.5 to 5.5 5.6 9.5 iddop(6) 3.0 to 3.6 3.6 6.0 iddop(7) ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 3.0 4.8 iddop(8) 4.5 to 5.5 0.76 2.8 iddop(9) 3.0 to 3.6 0.43 1.5 iddop(10) ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? 1/2 frequency division ratio 2.7 to 3.0 0.36 1.2 ma iddop(11) 4.5 to 5.5 48 140 iddop(12) 3.0 to 3.6 18 55 normal mode consumption current (note 9-1) (note 9-2) iddop(13) ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 14 40 a iddhalt(1) 4.5 to 5.5 4.3 7.6 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation stopped ? internal rc oscillation stopped ? usb circuit stopped ? 1/1 frequency division ratio 3.0 to 3.6 2.2 4.0 iddhalt(3) 4.5 to 5.5 8.1 15 iddhalt(4) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal pll oscillation mode active ? internal rc oscillation stopped ? usb circuit active ? 1/1 frequency division ratio 3.0 to 3.6 4.2 7.5 iddhalt(5) 4.5 to 5.5 2.7 4.8 iddhalt(6) 3.0 to 3.6 1.3 2.4 iddhalt(7) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to 6mhz side ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 1.1 1.8 iddhalt(8) 4.5 to 5.5 0.48 1.9 iddhalt(9) 3.0 to 3.6 0.22 0.81 halt mode consumption current (note9-1) (note9-2) iddhalt(10) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0hz(oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation. ? 1/2 frequency division ratio 2.7 to 3.0 0.17 0.57 ma note 9-1: the consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. note9-2: unless otherwise specified, the consump tion current for the lvd circuits is not included. continued on next page. LC87F1M16A no.a1909-26/32 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(11) 4.5 to 5.5 35 120 iddhalt(12) 3.0 to 3.6 9.5 39 halt mode consumption current (note 9-1) (note 9-2) iddhalt(13) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0mhz (oscillation stopped) ? fsx'tal=32.768khz crystal oscillation mode ? system clock set to crystal oscillation. (32.768khz) ? internal rc oscillation stopped ? 1/2 frequency division ratio 2.7 to 3.0 6.4 27 iddhold(1) 4.5 to 5.5 0.08 24 iddhold(2) 3.0 to 3.6 0.03 11 iddhold(3) ? hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.0 0.02 9.6 iddhold(4) 4.5 to 5.5 2.9 29 iddhold(5) 3.0 to 3.6 2.2 15 iddhold(6) ? hold mode ? lvd option selected ? cf1=v dd or open (external clock mode) 2.7 to 3.0 2.1 12 iddhold(7) 4.5 to 5.5 2.9 32 iddhold(8) 3.0 to 3.6 1.4 16 hold mode consumption current (note 9-1) (note 9-2) iddhold(9) ? hold mode ? watchdog timer operation mode (internal low-speed rc oscillation circuit operation) ? cf1=v dd or open (external clock mode) 2.7 to 3.0 1.2 14 iddhold(10) 4.5 to 5.5 31 110 iddhold(11) 3.0 to 3.6 7.0 34 timer hold mode consumption current (note 9-1) (note 9-2) iddhold(12) v dd 1 ? timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.7 to 3.0 4.3 22 a note 9-1: the consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. note9-2: unless otherwise specified, the consump tion current for the lvd circuits is not included. usb characteristics and timing at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol conditions min typ max unit high level output v oh(usb) ? 15k ? 5% to gnd 2.8 3.6 v low level output v ol(usb) ? 1.5k ? 5% to 3.6v 0.0 0.3 v output signal crossover voltage v crs 1.3 2.0 v differential input sensitivity v di ? ? (d+)-(d-) ? 0.2 v differential input common mode range v cm 0.8 2.5 v high level input v ih(usb) 2.0 v low level input v il(usb) 0.8 v usb data rise time t r ? r s =27 to 33 , c l =50pf ? v dd 3=3.0 to 3.6v 4 20 ns usb data fall time t f ? r s =27 to 33 , c l =50pf ? v dd 3=3.0 to 3.6v 4 20 ns f-rom programming characteristics at ta = +10c to +55c, v ss 1 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 ma tfw(1) ? erase operation 20 30 ms programming time tfw(2) ? write operation 3.0 to 5.5 40 60 s LC87F1M16A no.a1909-27/32 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator at ta = -40c to +85c circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0gh5l**-r0 (33) (33) 470 3.0 to 5.5 0.1 0.5 c1 and c2 integrated smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after v dd goes above the operating voltage lower limit. ? till the oscillation gets stabilized after the instruction fo r starting the main clock oscillation circuit is executed. ? till the oscillation gets stabilized after the hold mode is reset. ? till the oscillation gets stabilized after the x'tal hold mode is reset with cfstop (ocr register, bit 0) set to 0. characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 680k 2.7 to 5.5 1.1 3.0 applicable cl value=12.5pf smd type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 4): ? till the oscillation gets stabilized after the instruction fo r starting the subclock oscillation circuit is executed. ? till the oscillation gets stabilized after the hold mode is reset with extosc (ocr register, bit 6) set to 1. note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 crystal oscillator circuit rf rd2 xt1 xt2 c4 x?tal c3 rd1 cf1 cf2 c2 cf c1 LC87F1M16A no.a1909-28/32 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization time internal rc oscillation cf1,cf2 xt1, xt2 operating mode hold reset signal hold reset signal valid tmscf tmsx?tal hold halt power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd operating v dd lower limit gnd 0.5v dd LC87F1M16A no.a1909-29/32 figure 5 external filter circuit for th e internal usb-dedicated pll circuit figure 6 usb port peripheral circuit figure 7 sample reset circuit when using the internal pll circuit to generate the-48mhz clock for usb, it is necessary to connect a filter circuit such as that shown to the left to the p34/ufilt pin. after pll settings, 20ms or more is required to stabilize. rd 0k cd 2.2 note: it?s necessary to adjust the circuit constant of the usb port peripheral circuit each mounting board. make the d+ pull-up resistors available to control on/off according to the vbus. c res v dd r res res note: the external circuit for reset may vary depending on the usage of por and lvd. see ?reset function? in the user?s manual. 5pf 27 to 33 d- d+ 5pf 27 to 33 1.5k p70/ p27 vd3oen/ vd3oe2 LC87F1M16A no.a1909-30/32 figure 8 serial input/output waveform figure 9 pulse input timing signal waveform figure 10 usb data signal timing and voltage level tpil tpih data ram transfer period (sio0, 4 only) data ram transfer period (sio0, 4 only) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo t r t r d+ d- 10% 10% 90% 90% v oh v crs v ol LC87F1M16A no.a1909-31/32 figure 11 example of por only (lvd deselected) mode waveforms (at reset pin with r res pull-up resistor only) ? the por function generates a reset only when the power voltage goes up from the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function as shown below or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 12 example of por + lvd mode waveforms (at reset pin with r res pull-up resistor only) ? reset are generated both when power is turned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. figure 13 minimum low voltage detection width (example of voltage sag/fluctuation waveform) por release voltage (porrl) v dd res reset unknown area ( pouks ) (a) (b) reset p eriod reset period 100 LC87F1M16A no.a1909-32/32 ps this catalog provides information as of march, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. |
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